`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   18:32:48 07/02/2015
// Design Name:   Etapa5
// Module Name:   D:/Libraries/Documents/Ingenieria en computacion/Arquitectura Computadoras/TrabajoFinalArquitectura/trunk/Final-Mips/Etapa5Test.v
// Project Name:  Final-Mips
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: Etapa5
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module Etapa5Test;

	// Inputs
	reg [31:0] salidaE4;
	reg [4:0] salidaMux1;
	reg RegWrite1;
	reg MemToReg;
	reg jmp;
	reg [31:0] ALUdata;

	// Outputs
	wire [4:0] salidaMux;
	wire RegWrite;
	wire [31:0] salidaE5;

	// Instantiate the Unit Under Test (UUT)
	Etapa5 uut (
		.salidaE4(salidaE4), 
		.salidaMux1(salidaMux1), 
		.RegWrite1(RegWrite1), 
		.MemToReg(MemToReg), 
		.jmp(jmp), 
		.ALUdata(ALUdata), 
		.salidaMux(salidaMux), 
		.RegWrite(RegWrite), 
		.salidaE5(salidaE5)
	);

	initial begin
		// Initialize Inputs
		salidaE4 = 0;
		salidaMux1 = 0;
		RegWrite1 = 0;
		MemToReg = 0;
		jmp = 0;
		ALUdata = 0;

		// Wait 100 ns for global reset to finish
		#100;
        
		// Add stimulus here
		salidaE4 = 32'h 10101010;
		ALUdata = 32'h CBAE5CAB;
		#150;
		MemToReg = 1;
	end
      
endmodule

